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Download Sustained Simulation Performance 2012: Proceedings of the by Michael M. Resch (auth.), Michael M. Resch, Xin Wang, PDF

By Michael M. Resch (auth.), Michael M. Resch, Xin Wang, Wolfgang Bez, Erich Focht, Hiroaki Kobayashi (eds.)

The e-book offers the cutting-edge in excessive functionality computing and simulation on glossy supercomputer architectures. It covers developments in and software program improvement quite often and in particular the way forward for excessive functionality platforms and heterogeneous architectures. the appliance contributions conceal computational fluid dynamics, fabric technological know-how, scientific purposes and weather examine. cutting edge fields like coupled multi-physics or multi-scale simulations are awarded. All papers have been selected from shows given on the 14th Teraflop Workshop held in December 2011 at HLRS, college of Stuttgart, Germany and the Workshop on Sustained Simulation functionality at Tohoku collage in March 2012. ​

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RF/VAR” is energy consumption for the register file and vector arithmetic register file. “D$/VDR” is energy consumption for the on-chip cache, the vector data register, and the onchip network. “I$/Sched” is the energy for the instruction fetching and scheduling. “MEM” is the energy for off-chip memory access. We estimate the energy for processor chip only. Therefore, this estimation does not include any other device such as the inter-node interconnects For further investigation, we analyze the detail of the energy consumption.

Figure 5 shows the block diagram of the DGEMM-specialized Vector-SIMD processor. The processor employs 16-cores, 16-banked last-level cache, 4-channel DDR4 memory controllers, and the 2D-mesh on-chip network. 4 GB/s. These parameters are conservative, because the current processors have already realized these parameters. The challenge is the realization of the on-chip network having a 1 TB/s of bisection bandwidth with the 2D-mesh. Each core of the DGEMM-specialized Vector-SIMD realizes 640 GFLOPS with 256 FMAs, as shown in Fig.

As the hardware configuration of post Petascale computing systems is too complicated, this project will develop hierarchical abstraction layers to facilitate software development and future maintenance. In addition, we will establish a new concept of “HPC refactoring” for smooth migration of existing applications to the abstracted programming environment most important features characterizing this project. We will integrate the techniques developed in this project into a programming framework, called Xevoler.

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